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OEM Projects
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Mbps VDSL Private-Line Product. This design project was a ground-up
new-product architecture. The task involved the integration of
micro-processor, VDSL chipset, and custom FPGA technology to deliver a
complete stand-alone symmetric VDSL link that supports customer
connections of T1/E1, nX64K synchronous data, HSSI and 10 Mbps EtherNet
ports. Siliconexion managed both the hardware and software efforts on
this project.
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OC-12 ATM Network Access Product
Architecture. We worked with a Telecommunications client to propose
a complete architecture for an ATM access product that terminates,
transports, and routes native ATM, and IP over ATM to an OC-12 UNI. An
advanced Network Processor running at nearly 200 MHz handles most
routing functions centrally. Siliconexion is currently furthering this
project at the platform board hardware level.
Microwave
Phase-Locked Loop (PLL). Designed agile-frequency PLL control
subsystems (hardware and embedded firmware) for Microwave applications.
Embedded
Microcontroller Products. Designed various embedded
microcontroller circuit assemblies for microwave products. Developed
C-language software for application operator interfaces, serial
communication protocols, and real-time control functions.
Wireless Data Link.
Developed a 900MHz ISM-band wireless data link subsystem for remote
control applications, integrating the remote user interface into a
commercial handheld battery-power terminal/display device. Supported
the design with application-specific firmware
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ASIC/FPGA
Projects
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DSP Co-Processor in Xilinx
FPGA. Working with our customer’s Engineering team, we developed a
DSP co-processor to implement their proprietary wireless CDMA
algorithm. The design was targeted to a Xilinx XC40150XV for testing.
Subsequently, we participated with the customer on the integration of
this design with other cores into a single Xilinx XCV1000E target
device for later conversion to an ASIC device. |
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TDM-over-VDSL
solution in Xilinx FPGA. To achieve efficient transport of
synchronous and asynchronous traffic over inherently asynchronous xDSL
links required the design of special TDM framing, DPLL, and clock
recovery circuitry. With VDSL interface rates approaching 50 MHz,
Siliconexion was able to implement an entire TDM-over-VDSL hardware
solution in a single Xilinx Spartan II XC2S50 device.
Power Aware CPLD.
Designed a battery powered application with a Xilinx Coolrunner-2 CPLD
for . The design included power management functions, a microcontroller
interface and dual custom UARTs with receive flow control, a LCD
interface, and other control functions.
FPGA Design
Verification. Performed an independent FPGA design
verification of U S Navy mission critical commercial-off-the-shelf
(COTS) VMEbus cards.
RF Phase-Locked Loops. Designed N-integer and N-fractional digital
hardware control loops for RF Phase-Locked Loops and developed
associated application support, re-programmable software. Used both
CPLD and Analog Devices application-specific devices.
Programmable
Random Error and Delay. Designed hardware and developed FPGA
code for a 50Mbps, bi-directional Programmable Random Error and Delay
Simulator for serial data and telecom applications. The data buffer
requirement was met using a standard PC100 SDRAM memory module,
operating at 70MHz. All real-time logic functions including the SDRAM
controller were implemented in a Xilinx XC2S200 device.
FPGA Design and
Verification Training Classes. Offered custom tailored classes
from one to five days at client and other facilities.
- IEEE SouthCon
- Programmable Logic User Group
- Bechtel Bettis Atomic Power Laboratory
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